ASIC Verification Engineer Resume

ASIC verification engineer is a chip level testing engineer who performs the tasks of verifying designs by using directed and randomized testing from internal and external design sources. Some of the typical job profile of an ASIC verification engineer includes developing complex verification environments, chip level testing environment, verifying detailed functionality, developing and executing test plans. This position requires electrical engineering candidates with extensive knowledge of ASIC verification. Sound knowledge of standard verification methodology, Verilog, SystemVerilog, and random testing techniques are some of the essential requirements of the position.

When drafting a job application resume, keep in mind that the employer is looking for a suitable candidate. This means checking relevant skills, work exposure and education of the applicant. Do not write your resume as an autobiography. Take it as an advertising statement, precise and to the point. The purpose of your resume is to demonstrate that your are the suitable applicant that can meet the requirement listed in the job description. It should also display your interest and willingness to work in the position.

Below is an ASIC verification engineer resume that has been prepared for your reference:

ASIC Verification Engineer Resume Example

Career Objective:

Result oriented and dynamic professional with wide exposure in ASIC verification. Sound knowledge of verification tools and methodologies and logic design. Looking for a position as an ASIC verification engineer in a prestigious organization.

Summary of Credentials:

• Comprehensive knowledge of the methodologies and applications of advanced verification tools
• In-depth knowledge of the concepts of networking systems, analysis and techniques of code coverage
• Familiar with co-simulation hardware and software by using Verilog and System Verilog models
• Possess strong verification skills like random and advertising testing as well as debugging
• In-depth knowledge of debug tools, logic design concepts and stimulators like VCS and MTI
• Extensive knowledge of the methods and technologies of software design and programming
• Possess outstanding communication and problem solving skills

Work History:

ASIC Verification Engineer,
Mind Tsa, New York
Duration: May 2012 till date

• Handle the tasks of deploying latest verification methodologies and techniques for ASIC processor network
• Responsible for identifying, implementing and tracking test and code coverage against product features and test plans
• Perform responsibilities of developing random, critical, and application level tests to ensure full feature coverage
• Responsible for providing support to the design staff in debugging fixes and designing debugs
• Assigned the tasks of implementing verification methodologies like silicon support flow, traffic generators and interface protocol checkers
• Perform verification of functional coverage by applying System Verilog assertions

Junior ASIC Verification Engineer,
GS Engineering, New York
Duration: July 2008 to April 2012

• Assigned responsibilities of assisting verification staff in creating, running, debugging and tracking tests against test plans
• Performed the tasks of implementing stimulus and checking modules with the help of senior verification engineer
• Handled responsibilities of preparing and implementing detailed test plans for design modules
• Played active role in stimulation, verification coding, and review of modules
• Performed verification infrastructure and testing of products as well as new product development

Educational Qualifications:

• Electrical Engineering Graduate
  New York University in the year 2009

Reference:

On request.