Digital Design Engineer Resume

Digital design engineers have the responsibilities of designing and verifying system circuits, logic and implementing algorithms to ensure the product satisfies customer requirements. They are expected to understand the correct methods and procedures which can be used in the RTL or Digital system development. Apart from this, the engineers must come up with the best methods which will assist to verify the digital system before an approval for the complete system design is sought from the senior managers. An individual aspiring to work in this field must have substantial knowledge of Verilog design, must be aware of digital state machine architecture, logic design concept, and have the ability to verify ASIC digital circuits. To work in this profile, a master's degree in the relevant field can always be a plus point on the resume.

Sample Digital Design Engineer Resume

Bella M. Pollock
4450 NW 229th Avenue
Hillsboro, OR 97124
Phone: 800-971-2453
Email: bellapollock@anymail.com

Career Summary:

Highly-motivated individual with hands-on experience in static timing analysis, RTL design and scripting tests seeking a challenging position in designing Mixed Signal systems where I can use my knowledge and skills for to provide quality products and ensure organization's growth.

Summary of Skills:

Sound knowledge of computer architecture
Good experience with ASIC and FPGA Design Flow and preparing basic schematic for digital logic design circuits
In-depth knowledge of physical design and digital logic design
Proficient in programming languages – C++, CUDA, Python, and TCL
Clear understanding of concepts in VHDL and Verilog
Experienced in leading small technical teams and ability to give clear instructions to ensure timely completion of projects
Ability to do Static Time Analysis and perform Clock Tree Synthesis
Good organizational, communication and interpersonal skills

Work Experience:

Senior Digital Design Engineer
Intel Corporation, Hillsboro, OR
November 2016 – Present

Performing front-end RTL cleanup for clock stamping and caliber checks
Providing guidance to trainee employees and conduct weekly guidance sessions
Handling duties like inserting internal scan, executing ATPG and creating test vectors for minimizing ASIC fault coverage
Presenting idea of integrating Linux drivers for SATA peripheral core with Xilinx SoC FPGA's to managers
Creating HDL models and redesigning system architecture for improving speed and performance

Digital Design Engineer
Xilinx Incorporation Pvt. Ltd., Hillsboro, OR
April 2014 – November 2016

Wrote new test scripts in CUDA, Python and deployed these scripts to speed up the testing process
Managed relations with external vendors for maintaining the latest versions of CAD tools
Developed customized testing scripts for different products using physical tools like Primetime and TCL
Designed a basic Mealy State Machine model for Arbiter FSM machines that operate on Round Robbin algorithm and provides access to the memory controllers
Successfully edited existing modules in VHDL

Associate Digital Design Engineer
Delphi Automotive Systems, Hillsboro, OR
September 2012 – March 2014

Corrected flaws in design of key product and revised development strategy that reduced the production time by 25%
Performed timing analysis and Layout cleanup using tools like TCL and other internal tools
Handled development and functional verification of existing RTL Behavioral Models
Took initiative for writing a new rough draft of functional specification for USB core
Identified faulty power supply performance in the department and suggested its replacement measures during team meetings
Debugged software and firmware by testing every unit in isolation, identifying problems and fixing bugs
Presented a new design of Verilog

Internship:

Graduate Design Intern
Delphi Automotive Systems, Hillsboro, OR
February 2011 – August 2012

Played a vital role in the team responsible for analyzing performance architecture and studying power consumed by the products
Being an efficient member of the team handling design and development of Memory controllers for different processors
Handled CAN network management as well as verification and testing of adaptive control systems
Prepared notes on automation testing on vehicle simulators using C++ scripting
Responsible for creating internal and external documentation for company products

Education:

Master's Degree in Electrical Engineering
ABC University, Hillsboro, OR
2012

Reference:

On request.

Have a look at "Digital Electronics Engineer Resume"