Design Verification Engineer Resume
A design verification engineer validates circuit designs of various electronic products. His job is to ensure quality and performance of the product and verify circuit components. He participates in design review meetings and provides suggestions and recommendations for improvements. In case any product fails, he perform failure analysis and advise corrective action.
Employment for a design verification engineer are available with telecommunication, software, and companies that develop embedded processors. A job application to email or mail to any of these potential employers must be drafted carefully. Look at this sample here and compare it with your resume.
Design Verification Engineer Resume Example
Bernard K. Whitman
1339 Lynch Street
San Francisco, CA 94103
Phone: 925-219-0636
Email: bkwhitman@freemail.com
Career Objective:
To work as a design verification engineer with a company engaged in designing and developing personal computers, laptops, and other electronic devices where I can perform production verification.
Summary of Skills:
- Comprehensive knowledge of functional verification, networking,and interconnect protocols
- Extensive knowledge of Verilog verification, static timing analysis, Verilog modeling and EDA tools
- In-depth knowledge of Fibre Channel, Digital Logic Design, 40/100G Ethernet, and E language
- Excellent knowledge of the methodologies and techniques of design verification
- Familiarity with Windows application programs, programming languages and scripting languages
- Proficient in Verilog modeling and System Verilog designing
- Ability to troubleshoot technical issues with outstanding communication skills
Work Experience:
Design Verification Engineer
Cirrus Design Systems, San Francisco, CA
November 2012 - Present
- Enhance user experience through extensive product verification
- Participate in product development from inception to mass production
- Collaborate with design and marketing team and develop user-centric products
- Develop comprehensive test plans and new test architectures
- Identify and mitigate product risks by performing analysis and characterization
- Identify critical performance metrics and limits by analyzing statistical data
- Ensure products are thoroughly tested, validated and delivered in time
Junior Design Verification Engineer
Cadence Corporation, San Francisco, CA
April 2010 - October 2012
- Developed and executed test plans and procedures for old and new products
- Performed functional, stress, and systems testing and executed tests independently
- Participated in design and specification reviews and identified test tool requirements
- Tracked, found, and eradicated bugs in programs through careful observation
- Ensured quality and performance in product following design standards and guidelines
- Analyzed project specifications and determined technology requirements
- Reviewed design specifications and prepared design verification plan
Education:
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Bachelor's Degree in Electronic Engineering
Techies College, San Francisco, CA
2009
Reference:
On request.
